31 		LOG(4,("DAC2: no load detection available. reporting no CRT detected on connector #2\n"));  in nv_dac2_crt_connected()
62 		LOG(4,("DAC2: CRT detected on connector #2\n"));  in nv_dac2_crt_connected()
67 		LOG(4,("DAC2: no CRT detected on connector #2\n"));  in nv_dac2_crt_connected()
93 	LOG(4,("DAC2: Setting screen mode %d brightness %f\n", mode, brightness));  in nv_dac2_mode()
107 	LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK)));  in nv_dac2_mode()
117 	LOG(4,("DAC2: setting palette\n"));  in nv_dac2_palette()
132 		LOG(8,("DAC2: PAL write index incorrect after programming\n"));  in nv_dac2_palette()
147 			LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed  in nv_dac2_palette()
167 		LOG(4,("DAC2: Fixing DFP refresh to 60Hz!\n"));  in nv_dac2_set_pix_pll()
183 	LOG(4,("DAC2: current NV30_PLLSETUP settings: $%08x\n", DACR(NV30_PLLSETUP)));  in nv_dac2_set_pix_pll()
187 	LOG(4,("DAC2: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040)));  in nv_dac2_set_pix_pll()
201 		LOG(4,("DAC2: Not programming DFP refresh (specified in nvidia.settings)\n"));  in nv_dac2_set_pix_pll()
203 		LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk));  in nv_dac2_set_pix_pll()
214 		LOG(2,("DAC2: PIX PLL frequency should be locked now...\n"));  in nv_dac2_set_pix_pll()
238 	LOG(2,("DAC2: dumping current pixelPLL settings:\n"));  in nv_dac2_dump_pix_pll()
244 	LOG(2,("DAC2: divider1 settings ($%08x): M1=%d, N1=%d, P1=%d\n", dividers1, m1, n1, p1));  in nv_dac2_dump_pix_pll()
252 			LOG(2,("DAC2: divider2 is enabled, settings ($%08x): M2=%d, N2=%d\n", dividers2, m2, n2));  in nv_dac2_dump_pix_pll()
254 			LOG(2,("DAC2: divider2 is disabled ($%08x)\n", dividers2));  in nv_dac2_dump_pix_pll()
263 	LOG(2,("DAC2: phase discriminator frequency is %fMhz\n", f_phase));  in nv_dac2_dump_pix_pll()
264 	LOG(2,("DAC2: VCO frequency is %fMhz\n", f_vco));  in nv_dac2_dump_pix_pll()
265 	LOG(2,("DAC2: pixelclock is %fMhz\n", f_pixel));  in nv_dac2_dump_pix_pll()
266 	LOG(2,("DAC2: end of dump.\n"));  in nv_dac2_dump_pix_pll()
295 	LOG(4, ("DAC2: NV10/NV20 restrictions apply\n"));  in nv10_nv20_dac2_pix_pll_find()
331 		LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n",  in nv10_nv20_dac2_pix_pll_find()
338 		LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n",  in nv10_nv20_dac2_pix_pll_find()
407 	LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco));  in nv10_nv20_dac2_pix_pll_find()
437 	LOG(2,("DAC2: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n",  in nv10_nv20_dac2_pix_pll_find()