Lines Matching refs:lanes
92 FDITransmitter::EnablePLL(uint32 lanes) in EnablePLL() argument
104 value |= FDI_DP_PORT_WIDTH(lanes); in EnablePLL()
182 FDIReceiver::EnablePLL(uint32 lanes) in EnablePLL() argument
199 value |= FDI_DP_PORT_WIDTH(lanes); in EnablePLL()
247 FDILink::PreTrain(display_timing* target, uint32* linkBandwidth, uint32* lanes, uint32* bitsPerPixe… in PreTrain() argument
283 *lanes = (bps + (*linkBandwidth * 8) - 1) / (*linkBandwidth * 8); in PreTrain()
285 *lanes = ((read32(txControl) & FDI_DP_PORT_WIDTH_MASK) >> FDI_DP_PORT_WIDTH_SHIFT) + 1; in PreTrain()
287 TRACE("%s: FDI Link Lanes: %" B_PRIu32 "\n", __func__, *lanes); in PreTrain()
289 if (*lanes > 4) { in PreTrain()
327 FDILink::Train(display_timing* target, uint32 lanes) in Train() argument
343 Receiver().EnablePLL(lanes); in Train()
345 Transmitter().EnablePLL(lanes); in Train()
350 result = _AutoTrain(lanes); in Train()
352 result = _SnbTrain(lanes); in Train()
354 result = _IlkTrain(lanes); in Train()
356 result = _NormalTrain(lanes); in Train()
370 FDILink::_NormalTrain(uint32 lanes) in _NormalTrain() argument
413 FDILink::_IlkTrain(uint32 lanes) in _IlkTrain() argument
429 tmp |= FDI_DP_PORT_WIDTH(lanes); in _IlkTrain()
507 FDILink::_SnbTrain(uint32 lanes) in _SnbTrain() argument
524 tmp |= FDI_DP_PORT_WIDTH(lanes); in _SnbTrain()
637 FDILink::_ManualTrain(uint32 lanes) in _ManualTrain() argument
650 FDILink::_AutoTrain(uint32 lanes) in _AutoTrain() argument
661 buffer |= (lanes - 1) << 19; in _AutoTrain()